Plasma processing systems are used in the manufacture and processing of semiconductors, integrated circuits, displays and other devices or materials, to both remove material from or to deposit material on a substrate such as a semiconductor substrate. Plasma processing of semiconductor substrates to transfer a pattern of an integrated circuit from the photolithographic mask to the substrate, or to deposit dielectric or conductive films on the substrate, has become a standard method in the industry.
In semiconductor processing, where various types of films are etched, integration challenges and trade-offs still remain. Conventionally, a dielectric layer is patterned with openings for depositing conductive materials to form vertical contacts. During the patterning process, etch resistant photoresist layer and/or a hard mask layer is deposited over the dielectric layer, exposed to a selected pattern, and developed. The layered structure is then etched in a plasma environment where the patterned photoresist layer defines openings in the dielectric layer.
Following the etching step, photoresist remnants and etch residues (e.g., polymer debris) are frequently observed on the etched features and chamber surfaces. One of the integration challenges in plasma cleaning (also known as in-situ ashing), is to successfully remove photoresist remnants and etch residues, while avoiding erosion of surrounding layers. Known systems have used a one-step ashing process in which the bias applied to the substrate is maintained constant throughout the ashing process.
Halocarbon gases are commonly used in the etching of dielectric layers, such as oxides and newer SiOC-containing, low-k, dielectric materials. These gases are known to generate fluoro-carbon polymer etch products that can deposit on the internal surfaces of the process chamber, as well as on the substrate surface, during the dielectric etching process.
FIG. 1 shows a schematic cross-sectional representation of a one-step ashing process. During a conventional one-step ashing process for removing photoresist 106 from structure 100, fluorocarbon polymers are released/etched from the chamber walls (commonly referred to as a memory effect) and can attack underlying dielectric layer 104 and cap layer 102 (e.g., SiN, SiC), leading faceting 108 of the dielectric layer and cap layer loss 110, sometimes even punching through the cap layer 102 and attacking the underlying conductive layer (e.g., copper, not shown). This effect can be high at the edges of a wafer due to the high fluoro-carbon polymer concentration near the chamber walls. Alternatively, the structure 100 can also contain fluoro-carbon polymer deposits.
During a conventional one-step ashing process, photoresist can be removed in a hydrogen-containing plasma. To avoid post-ashing residue formation, some bias power is applied to the substrate holder. During this process, the fluoro-carbon deposits on the chamber walls from the preceding dielectric etch are also etched, releasing fluorine radicals in the plasma. As the bias is applied to the substrate holder, these fluorine radicals can erode the underlying dielectric film and consume the cap layer. By reducing the bias or applying zero bias, dielectric film erosion and cap layer consumption can be reduced but post-ashing residue can still be observed.
A conventional one-step ashing process that can result in the above chamber problems can involve the following plasma process conditions: Chamber pressure=50 mTorr, RF bias=150 W, and O2 flow rate=200 sccm.
In semiconductor manufacturing, the conventional one-step ashing process is frequently carried out in a process chamber where the internal chamber surfaces (and the substrate to be ashed) can contain fluoro-carbon-based polymer deposits from a preceding dielectric etching process. Alternatively, the one-step ashing process can be carried out in a process chamber that has been cleaned of polymer deposits from a prior etching process.